Skip to content
TrenchBoot
Specifications
Initializing search
TrenchBoot Issues
Home
Events and publications
Specifications
Documentation
Steering Committee
TrenchBoot FAQ
Community
TrenchBoot
TrenchBoot Issues
Home
Events and publications
Events and publications
Conferences
Upcoming Events
Publications
Specifications
Specifications
Secure Launch Specification
Documentation
Documentation
Getting started
Getting started
TrenchBoot hardware requirements
Linux Quick Start Guide
Installing TrenchBoot AEM in Qubes OS
Building and installing GRUB
Building and installing Linux
Troubleshooting
Hardware test matrix
For developers
For developers
Contributing to TrenchBoot
Code Repositories
Introduction to Late Launch
Developers Guide
Theory
Theory
TrenchBoot Use Cases
General Architecture
Glossary
Blueprints
Blueprints
Secure Launch Resource Table
TXT Grub Late Launcher
AMD Grub Late Launcher
AMD Secure Kernel Loader
Linux Late Launch Kernel
Xen Late Launch Hypervisor
Measured Secure Boot
PoC: coreboot with payload started through DRTM (AMD)
References
References
AMD64 Architecture Programmers Manual Volume 2 Ch15.27
Intel TXT Preliminary Architecture Specification
Intel TXT Software Development Guide
Steering Committee
Steering Committee
Community Meeting June 17 2021
TrenchBoot FAQ
Community
Specifications
¶
TrenchBoot developed specifications.
Secure Launch Specification